Design of Floating Point Arithmetic Unit using VHDL
The main objective of project is to design and verify different operations of floating point arithmetic unit (FPAU). We have designed a 64-bit AU which accepts two floating point 64 bits numbers and the code corresponding to the operation which it has to perform from the user. The AU performs the desired operation and generates the result accordingly. A pipeline floating point arithmetic unit (AU) design using very high speed hardware description language (VHDL) is introduced. The novelty of the AU is it gives high performance through the pipelining concept. Pipelining is a technique where multiple instruction executions are overlapped. In the top-down design approach, four arithmetic modules: addition, subtraction, multiplication, and division: are combined to form the floating-point AU. Each module is divided into smaller modules. Two bits selection determines which operation takes place at a particular time. The pipeline modules are independent of each other. All the modules in the AU design are realized using VHDL. Design functionalities are validated through simulation and compilation. After the coding was done, the synthesis of the code was performed using Xilinx-ISE. Test vectors are created to verify the outputs as opposed to the calculated results. Successful implementation of pipelining in floating point AU using VHDL fulfills the needs for different high-performance applications.
This Article is Research By Priya Susan Mathew, Amal Kurian Mathew, Amitha Saleem, Stephanie Ann Kuruvilla, Dhanusha P.B and published by IJSTE JOURNAL
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